1. Field of the Invention
The present invention relates to the field of Integrated Circuits (ICs), and particularly to methods and systems for IC testing.
2. Discussion of the Related Art
ICs are typically manufactured many at a time in the form of dies on a semiconductor material wafer. After manufacturing, the semiconductor wafer is diced, so as to obtain a plurality of individual IC chips.
Before being packaged and shipped to the customers, and installed in various electronic systems, the individual ICs need to be tested for assessing their functionality, and in particular for ensuring that they are not defective, that they respect prescribed specifications, and that they work properly. In particular, during the test, information regarding global or local physical faults (such as the presence of undesired short circuits and break-down events) of the IC integrated on each die are obtained, and, more generally, the proper operation thereof is detected (for example, by checking the waveform of one or more output signals of the IC in response to predetermined stimuli). Only those dies with ICs that meet predetermined requirements can proceed to the subsequent manufacturing phases (such as wire bonding, packaging and final testing).
According to a known testing technique, the IC dies are tested before the semiconductor wafer is diced into the individual chips. The test conducted at the wafer level is referred to as “wafer sort” or “Electrical Wafer Sort” (“EWS”).
For example, in case of non-volatile semiconductor memory devices (such as Flash memories) the EWS test is performed on each die on which the memory device is integrated, in order to assess the correct operation thereof, e.g. to detect possible defective memory cells.
For performing the test, a tester is used which is coupled to the semiconductor wafer containing the IC dies to be tested, by means of a probe card which is used for interfacing the semiconductor wafer to the tester.
The tester is adapted to manage signals that are employed for performing the test. Hereinafter, such signals will be referred to as “test signals” and are intended to include test stimuli (e.g., commands, addresses of memory locations of the memory device to be accessed in read or write, data to be written into the memory device) which are generated by the tester and which are sent, by means of the probe card, to each die to be tested, and test response signals (e.g., data read from the memory device) which are generated by the ICs integrated on each die under test in response to the received test stimuli. The test response signals are sent by the IC integrated on each die under test to the tester, which processes them to derive an indication of the proper or improper operation of the ICs in the dies under test.
Often (for example during the EWS), the electrical coupling of the probe card with the ICs on the dies to be tested, necessary for achieving the signals exchange, is accomplished through probes adapted to establish a physical (mechanical and electrical) contact with corresponding contact pads on the ICs. For this purpose, the probe card includes of a PCB (Printed Circuit Board), which is connected to a large number (even of the order of some thousands) of mechanical probes, which are adapted to physically contact input/output contact pads of each die to be tested.
However, this type of test system has several limitations.
For example, there is the risk of damaging the contact pads of the dies under test. As known, a contact pad includes of an enlarged metallization region of the IC; when the tip of the mechanical probes touches the pads, there is always the risk that one or more of the pads are damaged by scrubbing, and the likelihood that this happens increases with the number of probes.
Also, the parallel-testing capability is relatively low: indeed, when several dies at a time have to be tested, the number of mechanical probes significantly increases; fabricating probe cards with many probes is not an easy task, and the finite dimensions of the probes pose a physical limit to the density of probes per unit area.
Moreover, the higher the number of probes required, the more probable it is that the electrical contacts between the pads of the ICs under test and the mechanical probes are not good, and electrical discontinuities may take place, which affect the test results.
Furthermore, when the contact pads are very close to each other (a situation frequently encountered due to the constant increase in integration scale and size shrinking), it is very difficult to ensure a good physical contact of the mechanical probes with the contact pads. Such a problem is emphasized when the pads are small in size and/or a large number thereof is present on each die.
In addition, the mechanical probes are very expensive, thus producing probe cards with several probes negatively contributes to the increase of the overall cost of the test system, and eventually of the ICs.
The U.S. Pat. No. 7,546,501 describes a method and apparatus for using a device's power and ground terminals as a test and/or debug interface for the device. According to this patent, messages are modulated over DC voltages applied to the power terminals of a device to input test/debug messages to the device and output test/debug messages from the device. This allows a device to be tested and/or debugged without the device having any shared or dedicated test or debug interface terminals. However, since according to this solution the transmission of the input and output test/debug messages is performed with transmitters and receivers that are equal to each other, and since the ICs share the same resources for the communication with the tester, it is necessary to provide a message traffic policy for avoiding message collisions. Specifically, said message traffic policy provides for the introduction in each IC of a corresponding personal identifier and a group identifier; this operation is carried out during a preliminary test phase. This constraint heavily reduces the communication efficiency, sensibly increasing test time and test costs. The most penalized tests are those exploiting the scan chains, wherein data (test vectors and signatures) are transmitted and received at the same time, requiring thus a full duplex transmission for all ICs that are sharing the resources. In this case, indeed, only one single IC at a time may communicate with the tester (and, thus, be tested).